To optimally synchronize data across GPUs interconnected via NVLink, the network connectivity can be decomposed into distinct ring structures. For example, an $$8$$-GPU NVLink network can be organized into two separate rings: one ring utilizing double NVLink bandwidth and a second ring using regular bandwidth. This decomposition strategy avoids the bottleneck of the PCIe bus by allowing data to be synchronized directly between GPUs, maximizing the utilization of the high-speed aggregate bandwidth provided by the NVLink connections.

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Modern deep learning hardware often features bespoke network connectivity to handle large data transfers efficiently. For example, in an $$8$$-GPU server, each GPU typically connects to a host CPU via a PCIe link operating at around $$16$$ GB/s. Simultaneously, each GPU may have multiple NVLink connections to other GPUs, each capable of bidirectionally transferring data at much higher speeds (e.g., $$300$$ Gbit/s or roughly $$18$$ GB/s per direction). Because the aggregate NVLink bandwidth significantly exceeds the PCIe bandwidth, maximizing training efficiency requires specialized synchronization protocols that exploit this hardware architecture.

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