Hardware accelerators like Graphics Processing Units (GPUs) have distinct latency profiles tailored for massive parallelism. Accessing a GPU's Shared Memory takes about $$30$$ ns (roughly $$30$$ to $$90$$ cycles, which can increase with bank conflicts), while accessing its much larger Global Memory is slower, taking approximately $$200$$ ns ($$200$$ to $$800$$ cycles). When transferring $$1$$ MB of data to or from the GPU, dedicated high-speed interconnects like NVLink take roughly $$30$$ μs (achieving $$\sim 33$$ GB/s), compared to roughly $$80$$ μs over a standard PCIe 3.0 x16 link ($$\sim 12$$ GB/s). Additionally, instructing the GPU to launch a CUDA kernel from the host CPU incurs an overhead latency of about $$10$$ μs.

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Because GPUs possess significantly more processing elements than CPUs, they require vastly higher memory bandwidth to avoid starving their compute units. To satisfy this demand, GPU architectures employ two primary strategies. First, they utilize much wider memory buses, such as the $$352$$-bit-wide bus found on NVIDIA’s RTX 2080 Ti. Second, they rely on specialized high-performance memory chips. Consumer-grade accelerators typically use GDDR6 modules, offering over $$500$$ GB/s of aggregate bandwidth. In contrast, high-end server accelerators, like the NVIDIA Volta V100, use High Bandwidth Memory (HBM). HBM modules connect directly to the GPU on a dedicated silicon wafer, delivering massive speed but significantly increasing manufacturing costs. Consequently, while GPU memory is functionally similar to CPU memory, it is substantially faster but generally much smaller in capacity.

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