In deep neural networks, gradients are computed sequentially from the output layers back to the input layers during backpropagation. To improve distributed training performance, systems can begin synchronizing the gradients of the already-processed upper layers while the lower layers are still computing their gradients. This overlapping of communication and computation minimizes hardware idle time and accelerates the overall training iteration.

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Efficient multi-GPU training relies on two foundational data synchronization operations. First, parameters must be distributed to multiple devices and gradients must be attached, because without parameters it is impossible to evaluate the network on a GPU. Second, an allreduce function is required to sum parameters across multiple devices and broadcast the result back, ensuring consistency.

Data Synchronization in Multi-GPU Training

Dive into Deep Learning

In data-parallel training, after gradients are computed across multiple devices, they must be synchronized to update the model parameters. This synchronization can be implemented using centralized strategies, where all gradients are sent to a single GPU or the CPU for aggregation, or through distributed strategies, where gradients are partitioned and aggregated simultaneously across multiple GPUs to leverage the full bandwidth of hardware switches.

Parameter Synchronization Strategies

Overlapping Gradient Computation and Synchronization

Modern deep learning hardware often features bespoke network connectivity to handle large data transfers efficiently. For example, in an $$8$$-GPU server, each GPU typically connects to a host CPU via a PCIe link operating at around $$16$$ GB/s. Simultaneously, each GPU may have multiple NVLink connections to other GPUs, each capable of bidirectionally transferring data at much higher speeds (e.g., $$300$$ Gbit/s or roughly $$18$$ GB/s per direction). Because the aggregate NVLink bandwidth significantly exceeds the PCIe bandwidth, maximizing training efficiency requires specialized synchronization protocols that exploit this hardware architecture.

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