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RegNet Design Space

The RegNet architecture emerges from the AnyNetXE\textrm{AnyNetX}_E design space, which simplifies the generic AnyNet design by enforcing a set of easily interpretable principles. Specifically, it requires sharing both the bottleneck ratio (ki=kk_i = k) and the group width (gi=gg_i = g) across all stages ii. Furthermore, it mandates that both the network width (cic_i) and the network depth (did_i) must increase monotonically across successive stages, meaning cici+1c_i \leq c_{i+1} and didi+1d_i \leq d_{i+1}.

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Updated 2026-05-13

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