Multiple Choice

A development team is deploying a large Transformer model on a new, custom-designed hardware accelerator. They observe that the model's inference speed is significantly slower than expected. Profiling reveals that the primary bottleneck is not the raw computational speed of the accelerator, but the time spent moving data between different levels of its unique memory hierarchy. Which of the following strategies represents a hardware-aware optimization approach to directly address this specific data movement issue?

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Updated 2025-10-02

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