Beyond memory access, various CPU execution steps and software operations exhibit distinct latency profiles. Basic execution steps are extremely fast; for example, a floating-point addition, multiplication, or fused multiply-add (FMA) takes approximately $$1.5$$ ns (roughly $$4$$ cycles). Control flow errors, such as a branch misprediction, incur a pipeline flush penalty of about $$6$$ ns ($$15$$ to $$20$$ cycles). Thread synchronization mechanisms, such as a mutex lock or unlock, take roughly $$25$$ ns. In contrast, higher-level software operations require significantly more time; for instance, compressing $$1$$ KB of data using a fast algorithm like Google Snappy takes approximately $$3$$ μs.

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The microarchitecture of a CPU core defines its internal execution components. The front-end is responsible for loading instructions and using branch prediction to anticipate the control flow path. Assembly instructions are frequently decoded into lower-level microinstructions before being processed by the execution core. To maximize throughput, modern execution cores are highly parallel and capable of performing multiple operations simultaneously in a single clock cycle (e.g., up to $$8$$ simultaneous operations on the ARM Cortex A77), provided those operations can be carried out independently. Within the execution core, units specialize in different tasks; for instance, some are dedicated to integer operations while others are optimized for floating-point performance. Furthermore, to increase throughput, the processor might concurrently follow multiple code paths during a branching instruction and later discard the results of the unused branches. Because following incorrect paths wastes computational resources, branch prediction units on the front-end are critical for ensuring that only the most promising paths are pursued.

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