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Writing (NTM Architecture)
In the Neural Turing Machine (NTM) architecture, each write operation is decomposed into two parts: an erase phase and an add phase. Given an erase vector (whose elements lie in the range (0, 1)) and a weight vector emitted by the write head, the previous memory vectors are modified as follows: M_{t}^{sim}(i) leftarrow M_{t-1}(i)[1 - w_t(i)e_t] If both the weight and erase values at a location are equal to one, the memory is reset to 0; otherwise, the memory is partially erased or remains unchanged. After the erase step, an add vector is applied to update the memory: M_t(i) leftarrow M_{t}^{sim}(i) + w_t(i)a_t
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Updated 2026-06-13
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